1. Field of the Invention
The present invention relates to a method for planarizing insulating layers on semiconductor substrates and more particularly, relates to a method for etching back and planarizing the spin-on-glass (SOG) for Inter-Metal-Dielectric (IMD) layers using a two-step etch back process, and thereby forming a more uniform IMD layer.
2. Description of the Prior Art
In today's Very Large Scale Integration (VLSI) and Ultra Large Scale Integration (ULSI) on semiconductor substrates patterned multilayer conductors are used to electrically interconnect the semiconductor devices in, and on, the substrate. Inter-metal-dielectric (IMD) layers are used between the patterned conducting layers to provide insulation. To achieve high circuit density, high resolution photolithographic techniques and directional (anisotropic) plasma etching has now replaced wet etching to pattern the conducting layers. However, the accumulated effect of depositing and patterning these conducting layers, one patterned layer on top of the other, has resulted in irregular or substantially non-planar microscopic surface features on an otherwise microscopically planar substrate. This rough or irregular topography also results from other structures on the substrate, such as semiconductor devices formed in and on the substrate surface. The rough topography becomes substantially worse at later processing steps when the multilayer metallurgy is used to wire-up the discrete devices for integrated circuits.
This rough topography causes a number of processing problems. For example, the present day high resolution photolithography require more shallow depths of focus during optical exposure of the photoresist, and this leads to unwanted distorted photoresist images over the non-planar portions of the substrates. Another problem can occur during anisotropic plasma etching to define the conducting lines. Due to the directional nature of the etching, unwanted residual portions of the conducting layer, usually referred to as rails, can remain on the sidewalls of the underlying patterns which can then lead to interlevel shorts. In addition, the thinning of the narrow interconnecting metal lines over steps in underlying patterned layers during the deposition can result in low yield and early failure of the circuit. This is especially true at high current densities where electromigration of the metal atoms in the metal lines can lead to voids and open lines, or can result in extrusion of metal between the closely spaced lines leading to shorts.
One important approach of minimizing these topographic problems is to planarize the inter-metal-dielectric layer over the patterned conducting layer, thereby preserving the planar nature of the substrate surface on which the next level of patterned conductive layers are formed. This planarization requirement is particularly important at the number of patterned multilayer metal levels increase where the accumulative roughness of the surface topography can be quite severe.
Various methods have been used for planarizing the dielectric layers. For example, bias sputtered silicon oxide and biased plasma enhanced chemical vapor deposition (PECVD), have been used to partially planarize the layer. Another method is to deposit a low melting temperature, such as a phosphosilicate glass (PSG) or borophosphosilicate glass (BPSG) and then thermally anneal the substrate. More recently, new techniques using Spin-On-Glasses (SOG) are being used as part of the interlevel insulators to form the planar insulating layer.
The spin-on-glass is of particular interest because the deposition process and planarization is relatively simple and the process utilizes low cost equipment. For example, the insulating layer is deposited by spin coating a liquid precursor, similar to the spin coating application of photoresist. The layer is then dried to remove the solvents and baked on a hot plate or in an oven to cure the layer and to form an inorganic oxide by pyrolysis. The spin coating application of the liquid precursor composed of a solvent containing, for example, a silicate or siloxane polymer tend to fill in the recesses between the patterned metal areas being thicker than the coating over the metal areas, thereby essentially forming an insulator with a planar surface over the patterned conducting layer. One disadvantage of SOG is out-gassing of H.sub.2 O molecules or water that can cause erosion of the patterned conducting layer, especially the metal conductors. Therefore, it is common practice in the semiconductor industry to deposit a conformal silicon oxide (SiO.sub.2) barrier layer, such as a chemical vapor deposited (CVD) oxide, over the underlying patterned metal layer before coating the substrate (wafer) with SOG. The SOG is then blanket etched back to this first CVD oxide barrier layer over the metal areas leaving the SOG in the trenches between the patterned conducting layer, and forming an essentially planar surface. A second CVD oxide barrier layer is deposited on the SOG in the trenches and on the exposed first CVD oxide barrier layer over the patterned conducting layer. Contact openings for the next conducting layer are then etched only in the CVD oxide regions over the conducting layer, thereby avoiding the out gassing from the SOG. This type of planarizing process is described in U.S. Pat. No. 4,775,550, by Chu, et al, entitled "Surface Planar-ization Method For VLSI Technology".
Although the use of spin-on-glasses can provide an effective method for forming a planar insulating layer on multilevel metallurgies, it is important to etch back the SOG uniformly across the substrate. Unfortunately, the etch back uniformity can be quite poor for a number of reasons. For example, the initial SOG coating is typically nonuniform due to the spin coating inertia during coating being about 3 percent thicker at the wafer center for a 6000 Angstrom thick coating. Due to the etching characteristics (loading effect across the wafer) of a typical plasma etcher the etch rate at the center of the wafer is also slower by about 3 to 4 percent. Still another problem occurs when a high polymer etch chemistry is used to achieve good planarization over the bulk of the wafer surface. Typically a gas mixture is used, such as trifluoromethane (CHF.sub.3) and carbon tetrafluoride (CF.sub.4), to increase the etch selectivity of the underlying CVD oxide to the SOG. Although the selective etch compensates for the micro-loading effect when the SOG layer is etched to the CVD oxide barrier layer providing for the improved planarization, it also adversely effects the etch uniformity during the SOG etching by forming a polymer film 2 at the wafer center, as depicted in FIG. 1, and the poor etch back profile due to this polymer is shown in FIG. 2 by plotting the oxide loss (oxide etched off the wafer) in Angstroms as a function of distance across a 150 millimeter diameter wafer, as depicted by curve 4 in FIG. 2. The accumulative effect of the above non-uniformity contributors is typically between about 12 to 15 percent. Also shown in FIG. 3 by curve 7 is the correlation of the selectivity between the insulating barrier layer, such as a plasma enhanced CVD oxide, and the SOG as a function of the etch back uniformity across the wafer for the conventional CHF.sub.3 /CF.sub.4 plasma etch. The degradation in uniformity is clearly seen with improved selectivity.
This poor uniformity can adversely effect the product (chip) yield on the wafer by over etching alone the perimeter of the wafer while just clearing the SOG at the wafer center. For example, if the over etching erodes the underlying conducting layer, such as a tungsten metallurgy, redeposition of metal residue can result in electrical shorts. Therefore, there is still a strong need to improve the etch uniformity across the wafer while retaining the desirable attributes, such as the high selective etch of CVD oxide to SOG necessary for good planarization.